Fast Dynamic Power Comparison at the VHDL Netlist Level
نویسنده
چکیده
-An increasing constraint in implementing algorithms in digital signal processors is low power design. In order to avoid time consuming and uneconomic redesigning it is essential to optimise the sources of power consumption in the earliest possible stage in the IC design cycle. This paper presents CapCount, a novel high-level dynamic power estimation tool, operating as an add-on tool to Synopsys and providing an accurate dynamic power estimate in a reasonable time. The implementation of a new stopping criterion in this tool gained in speed improvement over 30% simulating large designs without compromising in accuracy. Key-Words: High-Level Dynamic Power Estimation, Monte Carlo Method, Netlist Level
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